Скачать или смотреть Simulating Cycle Accurate Processor - ARM , RISC-V

This video will walk you through the various steps involved in running a cycle accurate processor simulation model. The whole process starts of with the user selecting the target core to be built. It can be an ARM core, RISC-V core. In-Order or Out of Order.
Once we decide on the core, we will look at the parameters of the Processor and how it can be mapped or built on a simulation platform. VisualSim Architect has the configurable pipeline stages built and provided along the tool so that the user can reconfigure the parameters as they require.
This video explains different key parameters defined per pipeline stage and how these parameters are mapped from the Processor core specification (obtained from the vendor product documentation). As an Example, we have chosen ARM Cortex A77 (Out of Order) processor core and an in-order RISC-V core and have explained the different parameters and algorithms defined per pipeline stages.
We use the statistics obtained from the simulation to evaluate the performance of the core and to also evaluate the source code. If the results are not within acceptable range, then we reconfigure the parameters and re-run the traces until we get acceptable results. VisualSim Architecture also provides multi core simulation capabilities where the user can run regression tests (100s of simulations on the same model but with different parameter configurations) and choose the best configuration.
The user is also given access to the algorithms defined per pipeline stage. For example, if the user wishes to evaluate the efficiency of a custom branch prediction algorithm, then the user can update the branch predictor code while the remaining stages unchanged.

For more information, contact [email protected]
For trying out the tool and the model, register using the link below:
https://www.mirabilisdesign.com/downl...