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Circuit Description

4 - FFs JK type connected, JK terminals of each joined together and connected to logic 1 voltage, so that it works as T type FF. Intially all FFs are cleared to 0000

Pulses that we want to count are applied at the input of 1st FF only. Output of 1st FF taken from QA , it acts as Clk input to FFB . Output of FFB acts as clock input to FFC and so on.

Ist Clk pulse falls from high to low, QA toggles, its output changes from 0 to 1, if there are indicators connected, QA indicator glows, QB, QC, QD remain off. Truth table shows 0001 which is binary equivalent of decimal 1.

2nd Clk pulse falling edge causes QA to fall from 1 to 0, this triggers QB to rise from 0 to1. QB indicator lights while QA, QC, QD remain off. Truth table shows 0010, which is binary equivalent of decimal 2.

Counting progresses with each Clk pulse.

8th Clk pulse falls, QD toggles to 1, QD indicator lights while QA, QB, QC remain off. Truth table shows 1000 which is binary equivalent of decimal 8.

At the rising edge of 12th pulse, QC, QD outputs are 11. QC, QD indicators light while QA, QB indicators remain off. Truth table reads 1100 which is binary equivalent of decimal 12.

At the rise of 12th pulse QC, QD are 11, both 1s are connected at the input of a Nand gate, output from Nand gate is 0, this 0 goes on Cr terminal of each FF. At the fall of 12th pulse all FFs are cleared to 0000, which is the intial state of counter.
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FFs can also be cleared to 0000 by taking the output from QA, QB. At the rise of 12 pulse they both are 11, connected to Nand gate on left side of the diagram, output of Nand gate is 0, this 0 goes on the clear terminals of all FFs. At the falling edge of 12 pulse all FFs are cleared to 0000 and the count starts again.

If the frequency of input Clk pulses is 1200 KHz, output frequency will be 100 KHz (0.1 MHz).

Time taken by the inside circuit of FF to perform operation when it receives input pulse and provides the output is called Propagation Delay, it is in nano seconds.

If the propagation delay of FFC is 10 n s, and FFD has 50 n s time delay, FFC resets earlier while FFD takes more time to reset. Reseting becomes unreliable.

The problem of reseting is overcome by using Reset Latch. Latch cct. ensures that all FFs reset together irrespective of time delay.