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The HBM3 DRAM is optimized for high-bandwidth operation to a stack of multiple DRAM devices across a number of independent interfaces called channels. It is anticipated that each DRAM stack will support up to 16 channels. Figure 1 shows an example stack containing 4 DRAM dies, each die
supporting 4 channels. Each die contributes additional capacity and additional channels to the stack (up to a maximum of 16 channels per stack).
Each channel provides access to an independent set of DRAM banks. Requests from one channel may not access data attached to a different channel. Channels are independently clocked, and need not be synchronous.

The DRAM vendor may choose to require an optional interface die that sits at the bottom of the stack and provides signal redistribution and other functions. The vendor may choose to implement many of the logic functions typically found on DRAM die on this logic die. This standard does not explicitly require nor prohibit such a solution.
The division of channels among the DRAM dies within a stack is left to the vendor. Figure 1, with the memory for four channels implemented on each die, is not a required organization. Organizations are permitted where the memory for a single channel is distributed among multiple dies; however, all accesses within a single channel must have the same latency for all accesses. Similarly, vendors may develop products where each memory die can flexibly support 1, 2, 4 or 8 channels – enabling 16-channel configurations with stacks of 4 to 16 dies while keeping all data for a given channel on one die.
Since each channel is independent, much of this standard will describe a single channel. Where signal names are involved, families of signals belonging to a given channel will have the suffix a, b, …, p for channels a through p. If no suffix is present, the signal(s) being described are generic instances of the various per-channel signals.


Each channel consists of an independent command and data interface. RESET_n, IEEE1500 test port and power supply signals are common to all channels. A channel provides access to a discrete pool of memory; no channel may access the memory storage for a different channel. Each channel interface provides an independent interface to a number of banks of DRAM of a defined page size. See Channel Addressing.

Table 1 outlines the signals required for each channel, and Table 2 adds global signals that are required once per HBM3 device.


Pseudo channel (PC) divides a channel into two individual sub-channels of 32 bit I/O each, providing 256 bit prefetch per memory read and write access for each pseudo channel.
Both pseudo channels operate semi-independent: they share the channel’s row and column command bus as well as CK and R0 inputs, but decode and execute commands individually as illustrated in Figure 2.
Address PC is used to direct commands to either to pseudo channel 0 (PC = 0) or pseudo channel 1 (PC = 1). Power-down and self refresh are common to both pseudo channels.
Array access timings as listed in the table below are applicable for each individual pseudo channel. For example, an ACTIVATE to PC0 can be followed by an ACTIVATE to PC1 as shown in Figure 2.
However a subsequent ACTIVATE to PC0 can only be done after tRRD (PC0). For commands that are common to both pseudo channels (PDE, PDX, SRE, SRX and MRS) it is required that the respective timing conditions are met by both pseudo channels when issuing that command. Both pseudo channels also share the channel’s mode registers.
All I/O signals of DWORD0 are associated with pseudo channel 0, and all I/O signals of DWORD1 with pseudo channel 1.

To enable higher performance, HBM3 DRAMs exploit the increase in available signals in order to provide semi-independent row and column command interfaces for each channel. These interfaces increase command bandwidth and performance by allowing read and write commands to be issued simultaneously with other commands like activates and precharges. See Commands.