10 tips for writing a clear state machine in Verilog: A UART transmitter example.

Hi, I'm Stacey and in this video I go over 10 tips for writing a clear Verilog state machine!

Github Code:
https://github.com/HDLForBeginners/Ex...
State Machine good practices paper:
http://www.sunburst-design.com/papers...
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0:00 Intro
0:34 #1: Signal names should be self explanatory
1:07 #2: Don't assume input data is always valid
1:30 #3 Use module parameters for values that could change
2:37 #4 Use the state change for counter resets
4:20 #5 Intermediate signals don't need a state condition
5:30 #6 In the async always block, only next_state is driven
6:32 #7 Default state must be included
7:04 #8 Register next state into current state in the sync block
7:39 #9 Use next state and current state to detect state transitions
and anchor code
9:08 #10 Use an additional process to drive other signals
10:04 Recap
11:20 Outro

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