Скачать или смотреть Delay Testing in Integrated Circuits: Methodologies for Path Delay Fault Detection &HardwareSecurity

Paper Title
Delay Testing in Integrated Circuits: Methodologies for Path Delay Fault Detection and Hardware Security

Authors
Palanichamy Manikandan, Østfold University College, Norway

Abstract
As semiconductor technology advances, high-speed circuits are becoming more common, which increases the chance of delay faults that can disrupt circuit timing. This paper explores the important issue of delay faults and reviews different testing methods, particularly focusing on path delay fault (PDF) testing and its role in hardware security. Various delay fault models and test generation techniques were discussed. The experiments on benchmark circuits showed that this approach could achieve a 12.7% to 19.6% increase in detecting path delay faults in circuits affected by hardware Trojans. These results highlight the need for effective delay testing methods to ensure the reliability of integrated circuits. This work recommends future research to focus on creating more efficient test generation methods and integrating security measures into standard testing practices.

Keywords
Path delay fault (PDF) testing, test generation; path selection; hardware trojans (HT); HT detection

Abstract URL: http://aircconline.com/abstract/ijnsa...

Full Text URL: https://aircconline.com/ijnsa/V17N2/1...

Volume URL: https://airccse.org/journal/jnsa25_cu...