Скачать или смотреть RISC-V Power and Performance Management - Andrew Jones & Sunil V L, Ventana Micro Systems Inc.

RISC-V Power and Performance Management - Andrew Jones & Sunil V L, Ventana Micro Systems Inc.

This talk presents a high-level power and performance model for RISC-V. The ACPI specification chapters which the model is based on are presented as well as corresponding SBI extensions needed for platform support. The following SBI extensions will be presented: SRST (ratified) - enables power-off, which is an ACPI "Global State" transition, HSM (ratified) - enables ACPI's "Lower Power Idle" (LPI) states for CPU idle, SUSP (will be proposed) - enables ACPI's "Sleeping" states for system suspend, and CPPC (will be proposed) - enables ACPI's "Collaborative Processor Performance Control" for the OS to manage the performance of a logical processor on a contiguous and abstract performance scale. In addition to presenting the specifications, the current OpenSBI and Linux implementations will be demonstrated.