Скачать или смотреть RISC-V Vector Sail Model and Test Generation - Yifei Zhu & Xi Wang, RIOS Lab & Tsinghua University

RISC-V Vector Sail Model and Test Generation - Yifei Zhu & Xi Wang, RIOS Lab & Tsinghua University

RISC-V Vector (RVV) is an instruction-set architecture extension that provides RISC-V vectorization support. It enables RISC-V processors to process data arrays, alongside traditional scalar operations in the SIMD manner to enhance the performance via data-level parallelism. However, the complexity of vector processing units can lead to the ambiguity of the vector specification. As such, a new Domain-Specific Language (DSL) is desired to build a golden reference model that accurately describes the behavior of the instructions and registers of a given ISA. Driven by this motivation, RIOS Lab designs the golden model of RVV in Sail, which is a DSL designed for expressing the ISA semantics of distinct computer architectures. This model will be released by the end of this year as a part of the standard RVV release of RISC-V foundation. In addition, as it is necessary to verify the behavior of RVV instructions implemented in our Sail model, RIOS Lab will also introduce an open-source random architectural test generator named “Talon”. Talon is portable with the RISCOF infrastructures and the generated instruction patterns are configurable via YAML. This presentation will show the design of the RVV Sail model and current progress. It will also demonstrate our random test generator as well as the new characteristics in future work. This proposal yields a golden model of RVV program executions and takes an active role in supporting the growth and evolution of the RISC-V ecosystem.

For more info about RISC-V, a free and open ISA enabling a new era of processor innovation through open standard collaboration, see: https://riscv.org/