Скачать или смотреть Instruction Set Architecture (ISA) in a Real CPU

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  / rossmcgowanmaths  .

Next weeks video will be the Fetch Execute Cycle.

In this video we take Instruction Set Architecture out of the textbook and design it directly into a working CPU.

Using the RTM-16 as a real example, I show how instruction formats are chosen, how opcode bits are allocated, how addressing modes affect hardware wiring, and how operand structure shapes the datapath.

Rather than talking about ISA in abstract terms, we look at what actually changes inside the machine when you decide:

• 2-operand vs 3-operand instructions
• register encoding width
• opcode size
• addressing mode

You’ll see how ISA decisions constrain register interconnects.

This is where theory becomes engineering:
ISA design → instruction encoding → datapath structure → real hardware consequences.

Topics in this video include:

instruction set architecture (ISA)
instruction format design
opcode allocation
2-operand vs 3-operand tradeoffs
register encoding constraints
addressing modes in hardware
datapath implications
16-bit CPU architecture (RTM-16)
designing ISA into a real machine