CTS_S1_L1: Clock Tree Synthesis Introduction (Part 1)

Clock Tree synthesis is very important in PD FLow. Understanding of that's also very important.
In this lecture, we are going to discuss why we usually do CTS? What are the challanges during connecting clock source pin to clock of Flipflop?

Below are links of previous Lecture series which will help you to jump directly to understand some concepts.
CLK_L1: Clock Skew Introduction (Part 1 )    • CLK_L1 - Clock Skew Introduction (Par...  
CLK_L2: Clock Skew Introduction (Part 2 )
CLK_L3: Importance of Clock Skew in Timing Analysis (Part1)    • CLK_L3 -Importance of Clock Skew in T...  
CLK_L4: Importance of Clock Skew in Timing Analysis (Part2)    • CLK_L4 - Importance of Clock Skew in ...  
CLK_L5: Clock Skew and Hold Violation    • CLK_L5 - Clock Skew and Hold Violation  
CLK_L6: Clock Skew and Setup Violation    • CLK_L6 - Clock Skew and Setup Violation  
CLK_L7: Challange in Fixing Setup and Hold Violation Using Clock Skew (Part 1)    • CLK_L7-  Challange in Fixing Setup an...  
CLK_L8: Challange in Fixing Setup and Hold Violation Using Clock Skew (Part 2)    • CLK_L8- Challange in Fixing Setup and...  
CLK_L9:Fixing Large No of Hold Violation using Clock Skew (Part1)    • CLK_L9 - Fixing Large No of Hold Viol...  
CLK_L10: Fixing Large No of Hold Violation using Clock Skew (Part2)    • CLK_L10 - Fixing Large No of Hold Vio...