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Скачать или смотреть "PHOENIX : the first crypto-agile hardware solution for ML-KEM and HQC" by Antonio Ras

  • Grenoble Alpes Cybersecurity Institute
  • 2025-03-27
  • 163
"PHOENIX : the first crypto-agile hardware solution for ML-KEM and HQC" by Antonio Ras
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"PHOENIX : the first crypto-agile hardware solution for ML-KEM and HQC" by Antonio RAS, PhD student, LSCO Lab, CEA-LETI

Abstract :
The security of public-key cryptography protecting today's and future communications is threatened by the advent of quantum computers. To address this challenge, post-quantum cryptography is being used to design new cryptographic systems that are resistant to quantum attacks. The National Institute of Standards and Technology (NIST), leading the transition to quantum-secure cryptography, has already standardized the first Key Encapsulation Mechanism (KEM) based on Euclidean lattices, known as ML-KEM, and has identified three KEMs based on error-correcting codes, including HQC, as potential candidates for future standardization.

The relative immaturity of current post-quantum cryptosystems encourages a crypto-agile approach, ensuring security through an easy transition between systems. Smart crypto-agility requires identifying and implementing efficient resource-sharing strategies, which is particularly challenging when dealing with cryptosystems from different cryptographic families. Since the last update from the HQC team, polynomial multiplication has become the primary bottleneck of the algorithm. A state-of-the-art alternative to replace this operation is the Frobenius Additive Fast Fourier Transform (FAFFT), a type of FFT applied in the binary domain.

This presentation introduces PHOENIX, the first efficient crypto-agile hardware strategy for sharing polynomial multiplication operations in ML-KEM and HQC. Specifically, the two targeted operations for mutualization are the Number Theoretic Transform (NTT) for ML-KEM and the Frobenius Additive FFT (FAFFT) for HQC. To achieve agility, PHOENIX employs a hardware design called the SuperButterfly unit, which can be configured to execute all processing elements—known as butterfly structures—contained within the selected multiplication operations. Finally, the discussion will cover the cost of agility in terms of resource utilization and the performance of the selected cryptosystems when using PHOENIX in a real FPGA-based system-on-chip scenario.

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