Скачать или смотреть 🛠️ Verilog Testbench Generator with Bash | Automate Simulation & Debugging | PinE Training Academy

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Presenting an innovative tool for hardware designers and verification engineers:
🔧 Verilog Automatic Testbench Generator using Bash

📌 Developed by:
Aditya Singh
(Design & Verification Batch Trainee)

🚀 Project Overview
This Bash-based project simplifies and automates the process of compiling and simulating Verilog hardware designs using Icarus Verilog and GTKWave.

Instead of manually creating testbenches and compiling files, this tool does it all — and even generates a custom testbench automatically if one isn’t provided.

🔍 Workflow Highlights
✅ Run vatg script from terminal

📂 Select Verilog design file

🧪 Detect or auto-generate testbench

🔄 Simulate design using Icarus Verilog

📄 View logs and simulation history

🌊 Open GTKWave for debugging

📖 Access help with --help

❌ Safe Exit Option

🎯 Why You’ll Love This Project
No need to manually write a testbench

Ideal for beginners and professionals

Lightweight, fast, and highly portable

Saves simulation logs for review

Visual signal debugging via GTKWave

Supports error handling and guided help

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