Skymont E-core Architecture Explained by Intel Fellow | Talking Tech | Intel Technology

In this episode of Talking Tech, we’re joined by Stephen Robinson, Intel Fellow and Chief CPU Architect, who breaks down the front and back-end changes that bring additional versatility to Lunar Lake’s Efficient-cores, codenamed Skymont. Compared to the previous Crestmont generation, Skymont E-cores are deeper, wider, equipped with more L2 cache, and integrated with a fabric that provides access to a new memory side cache. The result is a highly performant low power island capable of running a wider range of workloads with excellent efficiency.

Watch the Intel Tech Tour Skymont live session recording here:    • Architecture All Access: Live at Luna...  

Lunar Lake architecture overview:    • Lunar Lake Overview: In-Depth With Le...  

Chapters:
00:00 – Intro
00:27 – E-cores through the years
01:40 – The low power island
02:42 – Memory side cache
03:29 – Expanding to more workloads
05:00 – A new microarchitecture
05:49 – 3x3 Decode cluster
08:04 – Vector performance
10:13 – AI workloads
11:37 – Scalability
12:42 – Thinking about E-core performance
15:13 – Conclusion

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