Скачать или смотреть How to Effectively Use Verilator with CMake for RTL with SV Packages

Discover how to address issues when using `Verilator` with `CMake` in RTL design that utilizes `SystemVerilog` packages. This guide provides useful tips and solutions for your testbench setup.
---
This video is based on the question https://stackoverflow.com/q/77585454/ asked by the user 'Jose Ruiz' ( https://stackoverflow.com/u/23021326/ ) and on the answer https://stackoverflow.com/a/77587683/ provided by the user 'Jose Ruiz' ( https://stackoverflow.com/u/23021326/ ) at 'Stack Overflow' website. Thanks to these great users and Stackexchange community for their contributions.

Visit these links for original content and any more details, such as alternate solutions, comments, revision history etc. For example, the original title of the Question was: Using Verilator with CMake when RTL uses a SV package

Also, Content (except music) licensed under CC BY-SA https://meta.stackexchange.com/help/l...
The original Question post is licensed under the 'CC BY-SA 4.0' ( https://creativecommons.org/licenses/... ) license, and the original Answer post is licensed under the 'CC BY-SA 4.0' ( https://creativecommons.org/licenses/... ) license.

If anything seems off to you, please feel free to write me at vlogize [AT] gmail [DOT] com.
---
How to Effectively Use Verilator with CMake for RTL with SV Packages

If you are looking to set up your Verilator testbench (TB) using CMake and are running into issues with registering system Verilog (SV) packages, this guide is for you. Many developers transition from traditional Makefiles to CMake for improved project management and integration with C++ libraries. However, the complexities can sometimes lead to unexpected challenges.

The Problem Statement

When porting a Verilator testbench from Make to CMake, several users have encountered a common problem: the TOP_MODULE parameter in the verilate command seems to be ignored, causing Verilator to generate files for the wrong module. Instead of generating Vtop_core.h (the desired top module), it defaults to the first item in the source files, leading to confusion and compilation errors.

Key Symptoms:

CMake command generated files for some_pkg instead of top_core.

The C++ testbench cannot be built as it expects a different header file.

Attempts to modify the order of rtl_sources leads to other failures due to RTL dependencies.

The Solution

After experimenting with the verilate command options, a critical solution was discovered: adding a PREFIX parameter to explicitly define the module name that should be used for the generated files.

Here’s the key step to successfully resolve the issue:

Step 1: Update Your CMakeLists.txt

Add the PREFIX parameter to your verilate command. This can be done as follows:

[[See Video to Reveal this Text or Code Snippet]]

Explanation of Changes

TOP_MODULE: This parameter signifies which module serves as the top level of the design hierarchy.

PREFIX Vtop_core: By adding this command, you instruct Verilator to generate a module prefix that corresponds to your designated top module, ensuring that files are generated correctly.

Further Notes

It is essential to recognize that while this workaround effectively resolves the immediate problem, it might not be the most conventional practice when integrating the system-verilog package in a CMake environment.

Documenting the solution in your project notes or code comments would be beneficial for future reference and for any other developers who may work on the project down the road.

Possible Next Steps

Testing: Run your build process again after implementing the changes. This should resolve the issues initially faced with file generation.

Explore More Resources: Since this was a basic setup, consider exploring more about CMake best practices with Verilator and SystemVerilog packages.

Community Involvement: Engage with the community forums or GitHub discussions for Verilator and CMake to find other developers who might have encountered similar issues.

Conclusion

Migrating from Make to CMake can be challenging, particularly in the context of using Verilator with SystemVerilog packages. By specifying the PREFIX parameter in your verilate command, you can overcome the file generation issues related to your top module. This guide should streamline your testbench setup process, saving you time and effort in your development journey.

If you continue to face any other challenges or have found additional solutions, be sure to share them with the community!