Скачать или смотреть 💻🧑‍🏫 MCU SoC Design with SERV Processor | RISC-V & LiteX FPGA Tutorial (RTL to Bitstream)

👥 Who Should Attend?
🎓 Students & Graduates curious about RISC-V, SoC design, and FPGA-based microcontrollers.
💼 Early-career professionals aiming to gain hands-on skills in RTL-to-bitstream flows using open-source tools.
🛠️ FPGA Engineers & Chip Designers exploring LiteX for automated SoC integration and deployment.
💡 Tech Enthusiasts & Makers eager to understand how the world’s smallest RISC-V CPU (SERV) works in practice.
📚 Educators & Researchers looking for practical teaching examples in open-source CPU and SoC design.

🔹 Why Attend?
🖥️ Learn RISC-V basics: the open-source CPU instruction set architecture.
⚙️ Discover SERV – the world’s smallest RISC-V CPU, ideal for MCU-class SoCs.
🛠️ Understand SoC design flows: manual RTL, vendor toolchains, and open-source frameworks.
🔗 Hands-on LiteX workflow: from Python-based SoC generation to FPGA deployment.
📟 Explore FPGA bitstream creation, UART/GPIO/Timer integration, and firmware execution.
🌍 Gain exposure to open-source collaboration, cost savings, and innovation opportunities.


Guests Bio : Anoushka Tripathi is introduced as a VLSI Engineer at Monk9Tech, India’s own semiconductor fab, where FPGA-based SoC design projects are being worked on. AryavartSemi was founded by her as an initiative to spread semiconductor awareness and to build a stronger tech community in India. Her internship was undertaken at DRDO SSPL, during which contributions were made to FPGA-based defense applications, strengthening hands-on expertise in system design. A vision to drive innovation in India’s semiconductor ecosystem is carried forward, with the aim of bridging advanced chip design with real-world impact.



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