Challenges in writing SDC Constraints

Описание к видео Challenges in writing SDC Constraints

Writing design constraints is becoming more difficult as chips become more heterogeneous, and as they are expected to function longer in the field. Timing and power can change over time, and constraints need to be adjusted to that changing context. Ajay Daga, group director for R&D at Synopsys, talks with Semiconductor Engineering about the challenges in pushing constraints down to different hierarchical portions of a design and how to minimize the size of those constraints and to reduce noise in the results.

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