Скачать или смотреть Scaling Open Compute: RISC-V, Chiplets, and Future of AI and Robotics | Yasuo ISHII | Tenstorrent

Scaling Open Compute: RISC-V, Chiplets, and the Future of AI and Robotics by Yasuo ISHII | RISC-V CPU Architecture Fellow | Tenstorrent Japan

RISC-V Day Tokyo 2026 Autumn 2025/12/4 14:00-14:30

This presentation explores how the RISC-V architecture and chiplet technology enable Tenstorrent to develop a wide range of computing platforms across diverse markets, including AI, automotive, and robotics. The presenter also addresses the challenges of building composable systems with chiplets. While the technology to build chiplets, such as UCIe, has matured significantly in recent years, there are still significant gaps in achieving interoperability among chiplets from different vendors. The presenter will highlight key interoperability issues that arise when integrating chiplets from different vendors and share the solutions Tenstorrent is pursuing to overcome these barriers.


Yasuo is a processor architecture expert who leads next-generation RISC-V CPU microarchitecture design, frontend optimization, and performance exploration. He has nearly 20 years of industry experience and extensive knowledge in high-performance processor design, including CPU frontends, branch prediction, instruction fetch, caches, and data prefetching.
Before joining Tenstorrent in 2023, he spent more than eight years at Arm as a Senior Principal Engineer, where he worked on CPU microarchitecture, frontend logic design, and performance analysis. At Arm, he played a key role in developing core technologies for advanced CPUs, including instruction fetch, branch prediction, and scheduling.
Prior to his roles at Tenstorrent and Arm, he worked for over eight years as a hardware engineer at NEC in Japan, contributing to CPU logic design across a wide range of frontend technologies, including instruction caches, decode units, scheduling, prefetching, and memory disambiguation.