Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial

Logic Synthesis is performed once the RTL code is simulated and verified. In Logic Synthesis, A RTL code is converted into a gate-level netlist of given standard cell library.
Logic Synthesis Flow using DC (Design Compiler of Synopsys) has been explained in this tutorial.

In this RTL-to-GDSII flow of video series, there is a total of 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow.

1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow
Video link:    • RTL to GDSII flow | Basic terminology...  

2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files
Video link:    • ASIC Flow and EDA tools | Various fil...  

3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo
Video link:    • RTL Design & Simulation | Synopsys VC...  

4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler
Video link:    • Logic Synthesis flow | RTL Synthesis ...  

5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist
Video link:    • Logic Synthesis of RTL | Synopsys Des...  

6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision
Video link:    • Logic Synthesis in Design Compiler | ...  

7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial
Video link:    • Logic Equivalence Check | Synopsys Fo...  

8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow
Video link:    • Physical Design Flow | PnR flow | RTL...  

9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial
Video link:   • Design Import | Cadence Innovus | GUI...  

10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo
Video link:    • Place and Route in Cadence  Innovus |...  

====Connect with us==========================
All on one page: https://www.teamvlsi.com/p/contact_8....
Blog: https://www.teamvlsi.com
Facebook Page:   / teamvlsi  
WhatsApp Group: https://chat.whatsapp.com/C6etLHR6oAf...
Telegram Group: https://t.me/teamvlsi (Or search team VLSI on telegram)
Email: [email protected]
==============================

#LogicSynthesis #DesignCompiler #LogicSynthesisFlow