FPGA 30 - Zynq SoC FPGA Direct Memory Access (DMA) between PS DDR memory and PL AXI4-Stream FIFO

In this episode, we're building a complete Zynq SoC FPGA application demonstrating direct memory access (DMA) in both directions between the processing system's DDR memory and another block of memory with an AXI4-stream interface residing in the programmable logic fabric.
The application is validated on the pynq-z1 board.

The DMA engine is configured by the C application through the AXI4-Lite interface to initiate DMA-read and DMA-write operations. In DMA-read operation, a block of 16 32-bit incrementing numbers is transferred from the DDR to the AXI4-Stream FIFO data buffer. That block of data from the AXI4-Stream FIFO is then moved back to the DDR at a different memory location through a DMA-write operation. The received data is then read and verified to validate the complete DMA application works as intended.

#fpga #zynq #vivado #vitis #embedded #verilog #xilinx

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