Скачать или смотреть SR FF NOR LATCH XOR || VERILOG_CODE

#SR_FF_NOR_LATCH_XOR

SOURCE CODE
module SR_FF_NOR_LATCH_XOR(q,qbar,s,r,clk);
output q,qbar;
input s,r,clk;
wire w1,w2;
xor x1(w1,s,clk);
xor x2(w2,r,clk);
nor n1(q,w1,qbar);
nor n2(qbar,w2,q);
endmodule

TEST BENCH
module SR_FF_NOR_LATCH_XOR_TB;

// Inputs
reg s;
reg r;
reg clk;

// Outputs
wire q;
wire qbar;

// Instantiate the Unit Under Test (UUT)
SR_FF_NOR_LATCH_XOR uut (
.q(q),
.qbar(qbar),
.s(s),
.r(r),
.clk(clk)
);

initial begin
// Initialize Inputs
s = 0;
r = 0;
clk = 0;

#100 s = 1;
#100 r = 1;
#100 clk = 1;

#100 s = 0;
#100 r = 0;
#100 clk = 0;

end
endmodule

SYNTHESIS REPORT:
Delay: 9.369ns

AUTHOR: T MAHARSHI SANAND YADAV
DESIGNATION: ASSISTANT PROFESSOR
https://docs.google.com/document/d/e/...