How to GaN 05a - Layout Techniques to Maximize Gallium Nitride (GaN) Device Performance

This video updates How to GaN 05 - Layout with information from the How2GaN Summer Webinar Series. https://epc-co.com/epc/EventsandNews/...

In this video, our GaN Experts will focus on high-performance layout techniques to maximize Gallium Nitride device performance.

Topics covered include:

Parasitic inductances and their impact on converter performance
Layout design comparisons
Designing a low inductance layout
Alternative layout configurations
Gate circuit layout
Working with single IC dual gate drivers
Considerations to add a source shunt


0:00 Start
0:05 Intro
0:48 Agenda
1:48 Parasitic inductance considerations
2:59 Impact of common source inductance
3:57 Impact of power loop inductance
5:21 Impact of gate loop inductance
6:22 Layout comparisons
11:13 Layout inductance comparisons
13:15 How to design a low inductance layout
17:52 How to minimize common source inductance in gate connection
22:44 Considerations for a source shunt
27:00 Source shunt layout
28:41 Layout summary and additional resources
30:46 Q&A session from live webinar


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