Скачать или смотреть VHDL Combinational and Sequential Design using Process blocks and Test Bench

VHDL is used to describe a simple combinational circuit feeding into a single flip flop. The circuit is accompanied by an exhaustive test. The VHDL is compiled with Xilinx Vivado 2015.2.

This entity has 5 inputs total (4 data inputs and one clock) and a single output; 4 inputs are sent through a 3 gate combinational logic circuit. The output of these gates are fed into a single D Flip Flop.

The process block can be placed in the module description to describe registers and flip flops (when the process is activated by a clock, for example the rising_edge() construct.)

A process can describe combinational logic by placing each of those driving signals in the sensitivity list; for example process(A,B,C) ....

Finally a process can be used to toggle signals such as in the test bench.