a12 A Digital Flow for Asynchronous VLSI Systems: Status Update

Abstract
We are developing an open-source EDA flow for asynchronous logic. Key parts of the flow are implemented using the Galois system for parallelization to reduce run-time requirements. We report on the current state of this flow, and some of the issues that we are exploring in order to improve the overall quality of results and expand the class of circuits that can be implemented using the flow.

Authors
Udit Agarwal [email protected] (University of Texas at Austin)
Samira Ataei [email protected] (Yale University)
Jiayuan He [email protected] (University of Texas at Austin)
Wenmian Hua [email protected] (Yale University)
Yi-Shan Lu [email protected] (University of Texas at Austin)
Sepideh Maleki [email protected] (University of Texas at Austin)
Yihang Yang [email protected] (Yale University)
Keshav Pingali [email protected] (University of Texas at Austin)
Rajit Manohar [email protected] (Yale University)