Dynamic Random Access Memory (DRAM). Part 2: Read and Write Cycles

This is the second in a series of computer science videos is about the fundamental principles of Dynamic Random Access Memory, DRAM, and the essential concepts of DRAM operation. This video covers stages of the read cycle and the write cycle including memory address multiplexing as a means of inputting the row address and column address separately, thereby keeping down the number of external pins needed for a memory module. The roles of the Row Address Strobe (RAS) and the Column Address Strobe (CAS) are described, as well as the Write Enable input, all of which are active low. This video describes the purpose of the column address decoder, which is used to assert a word line according to the row address, and the column multiplexer, and column demultiplexer which are used to select a particular sense amplifier during read and write operations. This video also includes simplified timing diagrams for DRAM read and write operations. In the videos that follow, you will find out more about the combinational logic used to construct a row address decoder, a multiplexer and a demultiplexer. You’ll also see how DRAM banks are organised, so that it is possible to store bytes and words rather than just single bits.