[FPGA 2021] HBM Connect: High-Performance HLS Interconnect for FPGA HBM

Young-kyu Choi, University of California, Los Angeles
Yuze Chi, University of California, Los Angeles
Weikang Qiao, University of California, Los Angeles
Nikola Samardzic, University of California, Los Angeles
Jason Cong, University of California, Los Angeles

With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applications to benefit from FPGA acceleration. However, fully utilizing the available bandwidth may not be an easy task. If an application requires multiple processing elements to access multiple HBM channels, we observed a significant drop in the effective bandwidth. The existing high-level synthesis (HLS) programming environment had limitation in producing an efficient communication architecture. In order to solve this problem, we propose HBM Connect, a high-performance customized interconnect for FPGA HBM board. Novel HLS-based optimization techniques are introduced to increase the throughput of AXI bus masters and switching elements. We also present a high-performance customized crossbar that may replace the built-in crossbar. The effectiveness of HBM Connect is demonstrated using Xilinx's Alveo U280 HBM board. Based on bucket sort and merge sort case studies, we explore several design spaces and find the design point with the best resource-performance trade-off. The result shows that HBM Connect improves the resource-performance metrics by 6.5×-211×.

ACM Digital Library: https://dl.acm.org/doi/10.1145/343192...



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