Harshith Mukunda

AES-128 HW/SW Co-Design on DE1-SoC FPGA | Hardware Acceleration & Verification
AES-128 HW/SW Co-Design on DE1-SoC FPGA | Hardware Acceleration & Verification
DE1‑SoC HPS‑FPGA HEX Clock – HPS‑Driven 7‑Segment Display (Homework 9 Part 2)
DE1‑SoC HPS‑FPGA HEX Clock – HPS‑Driven 7‑Segment Display (Homework 9 Part 2)
DE1‑SoC My_First_HPS‑FPGA Demo – HPS‑Controlled LED Shift (Homework 9 Part 1)
DE1‑SoC My_First_HPS‑FPGA Demo – HPS‑Controlled LED Shift (Homework 9 Part 1)
DE1-SoC HPS Peripheral Control: GPIO LED and Button Demo
DE1-SoC HPS Peripheral Control: GPIO LED and Button Demo
Optimizing Area vs. Latency in CyberWorkBench - EEDG 6370 Homework 7
Optimizing Area vs. Latency in CyberWorkBench - EEDG 6370 Homework 7
EEDG 6370 HW6 Part 4 - FPGA Prototype Demo
EEDG 6370 HW6 Part 4 - FPGA Prototype Demo
EEDG 6370 HW6 Part 1 - HLS Synthesis & Frequency Analysis
EEDG 6370 HW6 Part 1 - HLS Synthesis & Frequency Analysis
EE/CE 6370 - HW5 Part 4c: Modified VGA Output - Shapes (1280x720)
EE/CE 6370 - HW5 Part 4c: Modified VGA Output - Shapes (1280x720)
EE/CE 6370 - HW5 Part 1a: Basic VGA Output (1280x1024)
EE/CE 6370 - HW5 Part 1a: Basic VGA Output (1280x1024)
EE6370 Homework 4: FPGA Physical Design and Timing Analysis
EE6370 Homework 4: FPGA Physical Design and Timing Analysis
EEDG 6370 - HW3 Part II: 4x4 Multiplier with 7-Segment Display Output
EEDG 6370 - HW3 Part II: 4x4 Multiplier with 7-Segment Display Output
EEDG 6370 - HW3 Part I: 4x4 Unsigned Multiplier on DE1-SoC (LED Output)
EEDG 6370 - HW3 Part I: 4x4 Unsigned Multiplier on DE1-SoC (LED Output)
FPGA 10-LED Up/Down Counter on DE1-SoC
FPGA 10-LED Up/Down Counter on DE1-SoC
Full Adder Design and Analysis in Quartus Prime
Full Adder Design and Analysis in Quartus Prime
4-LED Up/Down Counter on DE1-SoC
4-LED Up/Down Counter on DE1-SoC