Скачать или смотреть EE6370 Homework 4: FPGA Physical Design and Timing Analysis

This video is a demonstration for Homework 4 in the "Design and Analysis of Reconfigurable Systems" (EE6370) course. It covers the process of synthesizing a Verilog design for a Terasic DE1-SoC FPGA and analyzing its timing performance using Intel Quartus Prime.

The demonstration includes:

Baseline Performance Analysis: Measuring the initial resource utilization, maximum frequency (Fmax), and the critical path delay of the compiled design.

Chip Planner Experiment: Using the Chip Planner to manually change the physical placement of logic elements and observing the significant impact on timing performance, highlighting the importance of interconnect delay.

FPGA Programming: Configuring the DE1-SoC board using an automated batch file that calls the Quartus programmer.

Tools Used:

Hardware: Terasic DE1-SoC (Cyclone V FPGA)

Software: Intel Quartus Prime Lite Edition