Creating input and output delay constraints

Hi, I'm Stacey, and in this video I discuss input and output delay constraints!

HDLforBeginners Subreddit!
  / hdlforbeginners  
Quartus Templates:
Found by navigating to Edit - Insert Template with a file open in the Quartus Prime Text Editor.
https://www.intel.com/content/www/us/...
Templates I used:
https://github.com/HDLForBeginners/Ex...
Digilent master XDC files:
https://github.com/Digilent/digilent-xdc
More advanced timing concepts in this altera paper:
https://www.intel.com/content/dam/alt...

Google form to give me your feedback:
https://forms.gle/ssNwzTKiioj3RNHD9

Ending music: Faith by David van Niekerk
   • Faith (Ocean of Reverb Original) - Da...  
I'm on discord on the r/fpga server (  / discord  , as Stacey, come say hi and chat all things FPGA!

Buy me a coffee to support my channel: https://www.buymeacoffee.com/fpgasfor...

0:00 Intro
0:07 Why we need these constraints
1:41 Compensating for trace lengths and why
2:40 Input Delay timing constraints
3:53 Output Delay timing constraints
4:23 Summary
5:53 Outro