Accelerate Functional Coverage Closure Using... - Robert Synoczek, Szymon Madej - code::dive 2023

Accelerate Functional Coverage Closure Using Co-simulation and Machine Learning

As designs become more complex, constrained-random verification has become insufficient to validate the design in a quick and efficient manner. Such techniques have serious limitations, and it has been proven that with complex designs it may prove difficult to achieve functional coverage closure in a reasonable time limit. The lack of appropriate techniques that could cope with modern complex designs turned attention of the researchers towards machine learning-based solutions. Those methods excel at finding patterns in data lakes and can be effective at improving the test generation process, making it more effective and less expensive. This presentation will cover the use of MATLAB in an example co-simulation and machine learning based random verification environment. It will include the basic concept and flow of a co-simulation based verification environment, as well as an introduction the issue of test selection in constrained randomized testing. The presentation will finish with an overview of the a autoencoder-based novel test selection system. This approach has been evaluated on a channel estimation block which is part of a 5G radio receiver, and the results show that it achieves up to 2x reduction in simulated tests compared to the traditional constrained-random test selection.

About the speaker - Robert Synoczek

FPGA Design Verification Engineer at the Nokia Kraków Research & Development. He works on innovative projects in the field of machine learning use in the design and verification of 5G telecommunications systems. He also conducts research in the field of machine learning implementations on SoC FPGA devices. He completed his masters studies in Automation and Robotics at the Faculty of Electrical Engineering, Automatics, Computer Science and Biomedical Engineering of the AGH University of Krakow.

About the speaker - Szymon Madej

FPGA engineer at Nokia Kraków Research & Development. He works on creating innovative projects in the field of machine learning and FPGA technology in telecommunications. He also implements scenarios for verifying new FPGA functionalities for 5G telecommunications systems using the SystemVerilog and UVM languages. He completed his engineering studies in Electrical Engineering at the Faculty of Electrical Engineering of the Wrocław University of Science and Technology.