Fanout & Embedded Packaging: Recent Advances and Future Trends

With the slowing down of Moore's law scaling, HPC systems today pursue heterogeneous integration of processor cores and memory chips on the same package. Hence, the bandwidth and power efficiency of chip-to-chip communication becomes the limiting factor in scaling system performance. Ravichandran’s research is on designing and demonstrating a novel 3D packaging architecture using glass-based panel embedding to achieve superior bandwidth and power efficiency than the current state-of-the-art silicon interposer packages in a low-cost and thermo-mechanically reliable fashion.

Lecturer: Siddharth Ravichandran, Ph.D. Candidate Georgia Tech ECE (Advisor: Rao Tummala - Endowed Chair & Professor Emeritus | GT ECE & MSE)