a04 A Push-button Idea to GDS-II SoC Design Flow

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Abstract
SoCGen is a system on chip (SoC) design automation tool that takes in a simple JavaScript Object Notation (JSON) description of the system’s components, connections and structure. The tool then outputs the Verilog HDL for the SoC, the intermediate files of hardening and the final GDS-II. SoCGen utilizes OpenLANE, an automatic RTL to GDS-II physical design flow. SoCGen is tailored for SoCs intended for internet of things (IoT) and deep embedded applications.

Authors
Habiba Gamal [email protected] (The American University in Cairo)
Amr Gouhar [email protected] (eFabless)
Mohamed Shalan [email protected] (The American University in Cairo)

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