JCET: Semiconductor Packaging and Testing, the State of the Art

Yaojian Lin, VP of Engineering and General Manager of R&D Center, JCET Group



Speech Title: Packaging Fundamentals of High-Performance Applications

• Si node technology in IC scaling is becoming too expensive, and associated yield can be problematic, and moreover, each node does not seem to provide the proportional performance and power benefits. In this context, the advanced packaging options have been surfaced out as an alternative. One option is to integrate heterogeneous dies in an advanced package, which can be called ‘chiplets’. From the OSAT standpoint, these chiplets is part of multi-die processing.

• Widespread adoption of 2.5D in price-insensitive markets such as chips for servers and network switches. On the other hand, the fan-out option can be a much simpler approach to heterogeneous integration than 2.5D in that chips basically can be pushed closer together on a board and then packaged.

• In this talk, the fundamental processes to be considered can be discussed.